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Xilinx Spartan-6 FPGA XC6SLX45T Daughter Board

The D.Module2.6SLX45T is based on the Xilinx Spartan-6 FPGA XC6SLX45T. In the D.Module2 family it can be used to implement additional interfaces or as a data preprocessing engine if hooked between a data acquisition card and a DSP module.
Up to 96 single-ended or 48 differential I/O signals are available. Programmable I/O voltages and I/O standards provide glueless system integration. Three gigabit transceivers are available to interface high-speed data converters in JESD204 standard, or as PCI/e or SATA interfaces. All D.Module2 DSP boards support a parallel bus interface to the D.Module2.6SLX45T. Depending on the DSP capabilities, alternative interfaces can be used: Link Ports, Serial Rapid IO, VLYNQ, or Fifo-based interface such as UPP or Video Ports.
The D2.Base-FMC base board provides an interface and a test and evaluation platform for FPGA Mezzanine Cards conforming to the Vita.57 LPC FMC standard.
≫ FPGA - Xilinx Spartan-6, XC6SLX45T
≫ Memory(DDR3) - 128M bytes, DDR3-1066
≫ Configration (SPI Flash Memory) - 8M bytes
≫ Clocks(onboard) - Si5338 clock synthesizer, I²C programmable, generates AUXCLK and GTP reference clocks.
≫ Clocks(external) - 16 single-ended / 8 LVDS global clock inputs
≫ DSP Board Interface(parallel) - 32 data bits, 20 address lines, 10 control lines, synchronous pipelined and/or asynchronous operation (depending on DSP capabilities)
≫ DSP Board Interface(serial) - 1 x Link Port (with D.Module2.TS203), 1 x SRIO, one lane, up to 3.125Gb/s, 2 x McBSP / SPORT port
≫ Programming Interface - JTAG via Xilinx Programming Cable, I2C via DSP board
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VP : T5404D1, Last updated :2018-02-14 16:29:48