The D.Module2.C6657 is based on the Texas Instruments Keystone dual-core processor TMS320C6657. The Keystone multicore DSPs are characterized by huge computational power and fast serial interfaces. The D.Module2.C6657 is perfectly suitable for radar applications, nondestructive material inspection, machine vision and software defined radio (SDR). An optional FPGA for data preprocessing is easily interfaced through Serial Rapid IO (SRIO), PCI express (PCIe) or via the fast Universal Parallel Port (uPP). Gigabit Ethernet enables network integration for control, remote maintenance and data streaming.
≫ DSP - TMS320C6657 dual-core 1.25 GHz fixed- and floating-point, up to 40 GMAC / 20 GFLOP per core
≫ Memory (DSP-internal) - 32K bytes data cache, 32K bytes program cache per core, 1M byte direct mapped or level-2 cache per core, 1M byte shared RAM
≫ Memory (DDR3) - 512M bytes, DDR3-1333, 32-bit wide
≫ Memory (Flash) - 8M bytes NOR (SPI interface, sector architecture), 64M bytes SLC NAND
≫ Ethernet (1000Base-T, 100Base-Tx, 10Base-T) - onboard PHY and magnetics, 1000Base-Fx Fiber support with external transceiver
≫ USB - USB1.1 12 Mbit/s